A complementary metal oxide semiconductor (“CMOS”) imager is a low cost imaging device. Typically, a CMOS imager includes a light sensor array composed of pixels. Light from a scene is received by each sensor or pixel in the array. Each pixel outputs an electrical signal that corresponds to the intensity and wavelength of the light received. The electrical output of each pixel in the array may be digitized and then combined to create a digital representation of the scene. CMOS imagers may be used, for example, in cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, auto focus systems, star trackers, motion detection systems, image stabilization systems and in other imaging systems.
Many CMOS imaging applications require high-resolution reproductions of imaged scenes. In order to maintain an optimal quality and brightness of an image, a CMOS imager must be capable of adjusting both exposure and gain settings for the pixel array to account for varying light conditions. Exposure relates to the time duration for which the array is capturing photons and accumulating induced electrons. Gain relates to the amount of analog amplification or attenuation that a pixel signal of the array undergoes. Amplification refers to a gain that is greater than one; attenuation refers to a gain that is less than one.
By varying the exposure and the gain of the array pixels, optimal images can be obtained from the pixel. For example, for the bright light conditions of a beach on a sunny day, an imaging device might adjust the image exposure to a minimum and the pixel gain to less than or equal to one. Similarly, acquiring an image of a polar bear in a snow storm might also require the image exposure be set to a minimum and the gain to less than or equal to one. On the other hand, in dark conditions such as when trying to capture an image of a deer at night, the image exposure might be adjusted to a maximum and the gain to greater than or equal to one.
One method used in automatic exposure control algorithms in an attempt to determine the best exposure setting for an image is to use a histogram. A histogram, in this case, depicts the number of pixels with the same pixel value for each possible pixel value in an image. For example, FIG. 1A depicts a 5×5 pixel array 101. Each pixel 102 has a digital value based on the scene imaged by the pixel array 101. The digital value of each pixel 102 is ‘n’ bits, meaning that each pixel 102 may have one of 2n digital values. The greater ‘n’ is, the greater the digital resolution of each pixel 102. An ‘n’ equal to 1 means that each pixel only has a maximum resolution of 21 values. In other words, in a grayscale pixel where ‘n’ equals 1, the pixel can only be one of two values, black or white. However, if ‘n’ is greater than 1, the pixel can be either white, black, or some other shade of gray. The higher ‘n’ is, the greater the number of shades that may be represented by a pixel. Hence, ‘n’ defines the digital resolution of a pixel.
An example of a histogram 110 of the pixel values in pixel array 101 is shown in FIG. 1B. In FIG. 1B, ‘n’ is 8. Thus, histogram 110 has 2n, or 28 bins along its horizontal axis, the bin numbers ranging from 0 to 255. Each bin represents a possible digital value for one or more pixels 102 in pixel array 101. The histogram 110 is populated by indicating in each bin the number of pixels 102 from the pixel array 101 having digital values corresponding to each respective bin number.
Once the histogram 110 is populated, the histogram 110 may be analyzed to determine if the image exposure needs adjustment. In general, an optimum exposure setting will result in a histogram with a broad distribution of pixel values across the range of the bins. In contrast, a histogram where the majority of pixel values are in the upper ranges of the histogram indicates that the image is over-exposed as too many pixels have large output signal values and the exposure time should be reduced, thus creating a broader distribution of pixel values within the histogram. A histogram where the majority of pixel values are in the extreme lower ranges of the histogram indicates that the image is under-exposed and the exposure time should be increased. An example of an algorithm for adjusting the exposure time based on the distribution of pixel values within a histogram is described in U.S. patent application Ser. No. 10/661,551, published as U.S. 2005/0057666, herein incorporated by reference in its entirety.
An automatic exposure adjustment algorithm such as explained in the '551 application may be implemented as an auto-control feedback loop. FIG. 2 is a block diagram of an auto-control feedback loop 200. The pixel array 201 accumulates charge based on an exposure to light from a scene. Exposure registers in a register circuit 210 control the exposure of the pixel array 201. The accumulated charge within each pixel in the pixel array 201 is sent as a digitized image stream 215 from the pixel array 201 to the automatic exposure control circuit 220. The automatic exposure control circuit 220 creates a histogram and evaluates the same and then updates one or more exposure registers in the register circuit 210 via a feedback stream 225. This process may repeat until a desired exposure setting is obtained for array 201.
Returning again to FIG. 1B, histogram 110 is represented as a full histogram, meaning that histogram 110 has a bin for each possible pixel value and each bin has a bin capacity large enough to accumulate a count representing every pixel 102 in pixel array 101. In the example of FIG. 1B, each bin has the capacity to represent all 25 (5×5) pixels 102. In other words, each bin has a bin depth of 5 bits, where 25 is the next greatest power of two greater than 25. In hardware terms, creating a full histogram for the example of FIG. 1B requires 256 5-bit bins or 1,280 registers (256×5 registers). If each register is implemented by 8 gates, the total number of gates required is 10,240 gates. If the example were changed from a 5×5 pixel array to a typical quarter video graphics array (“QVGA”) image of 320×240 pixels, then a full histogram with 8-bit pixel values and maximum bin depth would require 256 17-bit bins. In this case, the full histogram would require 4,352 registers or 34,816 gates.
Clearly, generating a full histogram multiple times for each image tested during an automatic exposure operation requires a large amount of hardware resources and processing time. One method for reducing the hardware and processing demands is to not use a full histogram. Instead of generating a bin for each possible digital pixel value (e.g., ‘n’ equals 8 in the example above), the bin count is alternatively based on, for example, the ‘x’ most significant bits of a pixel's digital output. If for example, a pixel's digital output was 10 bits long (normally requiring a histogram with 210 or 1,024 bins), one could construct a reduced histogram using only the most important ‘x’ bits of each pixel output, where ‘x’ might be 6 or 7 (thereby only requiring 64 or 128 bins, respectively). Though the resolution of the resulting exposure measurement and control is thus somewhat reduced, the resulting savings in hardware and processing time is significant.
Another method for reducing the size of storage requirements for the histogram is to reduce the bin depth to only a small percentage of the total possible bin depth. Instead of making each bin capable of representing every single pixel in the pixel array, the bins are only made capable of holding a small percentage of the total number of pixels. For example, using a 90th percentile scheme, a bin need only hold 10% of the total number of pixels. Using a 99th percentile scheme, a bin need only hold 1% of the total number of pixels. In each scheme, a target bin is defined. A 90th percentile target bin represents the bin at which, in the ideal image, 90% of all pixels fall below or, in a histogram, to the left of the target bin and only 10% of all pixels fall in or above (to the right) of the target bin. The number of pixels in each bin is counted and summed, beginning at the highest or right-most bin (the bin that represents the most white pixels). Once the summed bin count equals 10% of the pixels, pixel counting may stop and a determination as to the image exposure setting may be made. If the 10% pixel count is arrived at within a bin that is higher than the target bin, a controller concludes that there are too many pixels in the higher ranges of the histogram and the image is over-exposed; the image exposure setting is adjusted accordingly. Similarly, if the 10% pixel count is arrived at within a bin that is lower than the target bin, the controller concludes that the image is under-exposed and the image exposure setting is adjusted. The goal is to find an image exposure setting that results in 10% of the pixels having values above the defined target bin. A similar scheme may be defined using the 99th percentile, where the focus is only on the highest valued 1% of the pixels.
Because only a small percentage of the pixels are actually counted in either the 90th or the 99th percentile schemes, the histogram bin depths are reduced accordingly. In a 90th percentile scheme, each bin need only have a bin depth of 10% of the total number of pixels. In a QVGA image, each bin need only be capable of storing 10% of the pixels of a 320×240 array. In other words, only 13 bits per bin are necessary (213 is the first power of two greater than 0.10(320×240)). For a 99th percentile scheme, only 10 bits per bin are necessary. With 8 gates per register, a 99th percentile scheme with ‘x’ equal to 7 requires only 10,240 gates.
In addition to the above-described solutions, greater hardware and processing time savings are still desired.